| Pin | Name | I/O | Description |
| 1 | D4 | I/O | databus bit 4 |
| 2 | D3 | I/O | databus bit 3 |
| 3 | D2 | I/O | databus bit 2 |
| 4 | D1 | I/O | databus bit 1 |
| 5 | D0 | I/O | databus bit 0 |
| 6 | AS | O | address strobe, information on address bus is valid (for asynchronous bus control)) |
| 7 | /UDS | O | upper data strobe (selecting bit 15 to bit 8 of databus) (for async. bus control)) |
| 8 | /LDS | O | lower data strobe (selecting bit 7 to bit 0 of databus) (for async. bus control)) |
| 9 | R or /W | O | read/write in combination with UDS and LDS to address of addressbus (for async. bus control) |
| 10 | /DTACK | I | data transfer acknowledge, signal indicating data transfer completion (for async. bus control) |
| 11 | /BG | O | bus grant, signals bus master devices that bus control can be given |
| 12 | /BGACK | I | bus grant acknowledge, indicates that some other device is bus master |
| 13 | /BR | I | bus request, indicates that a device needs to become bus master |
| 14 | Vcc | I | +5 Volts DC |
| 15 | CLK | I | clock signal (7.15909 MHz on NTSC systems (USA), 7.09379 MHz on PAL (Europe)) |
| 16 | Ground | I | Ground |
| 17 | /HALT | I/O | halt signal, signals processor to stop bus activity |
| 18 | /RESET | I/O | reset signal, in combination with halt it resets the amiga |
| 19 | VMA | O | valid memory address, indicates to MC6800 peripheral device that a address is valid |
| 20 | E | O | standard enable signal for MC6800 peripherals (10 MC68000 clocksignals, 6 low, 4 high) |
| 21 | /VPA | I | valid peripheral address, indicates that the device or memory area addressed is a MC6800 device |
| 22 | /BERR | I | bus error signal (wrong address to read or hardware failure) |
| 23 | /IPL2 | I | interrupt pending level bit 2, indicates priority level of the device requesting an interrupt |
| 24 | /IPL1 | I | interrupt pending level bit 1 |
| 25 | /IPL0 | I | interrupt pending level bit 0 |
| 26 | FC2 | O | function code, indicates the mode (user or supervisor) of processor |
| 27 | FC1 | O | function code |
| 28 | FC0 | O | function code |
| 29 | A1 | O | address bus bit 1 |
| 30 | A2 | O | address bus bit 2 |
| 31 | A3 | O | address bus bit 3 |
| 32 | A4 | O | address bus bit 4 |
| 33 | A5 | O | address bus bit 5 |
| 34 | A6 | O | address bus bit 6 |
| 35 | A7 | O | address bus bit 7 |
| 36 | A8 | O | address bus bit 8 |
| 37 | A9 | O | address bus bit 9 |
| 38 | A10 | O | address bus bit 10 |
| 39 | A11 | O | address bus bit 11 |
| 40 | A12 | O | address bus bit 12 |
| 41 | A13 | O | address bus bit 13 |
| 42 | A14 | O | address bus bit 14 |
| 43 | A15 | O | address bus bit 15 |
| 44 | A16 | O | address bus bit 16 |
| 45 | A17 | O | address bus bit 17 |
| 46 | A18 | O | address bus bit 18 |
| 47 | A19 | O | address bus bit 19 |
| 48 | A20 | O | address bus bit 20 |
| 49 | Vcc | I | +5 Volts DC |
| 50 | A21 | O | address bus bit 21 |
| 51 | A22 | O | address bus bit 22 |
| 52 | A23 | O | address bus bit 23 |
| 53 | Ground | I | Ground |
| 54 | D15 | I/O | databus bit 15 |
| 55 | D14 | I/O | databus bit 14 |
| 56 | D13 | I/O | databus bit 13 |
| 57 | D12 | I/O | databus bit 12 |
| 58 | D11 | I/O | databus bit 11 |
| 59 | D10 | I/O | databus bit 10 |
| 60 | D9 | I/O | databus bit 9 |
| 61 | D8 | I/O | databus bit 8 |
| 62 | D7 | I/O | databus bit 7 |
| 63 | D6 | I/O | databus bit 6 |
| 64 | D5 | I/O | databus bit 5 |
