NAME REG.ADR$ CHIP R/W P/D FUNCTION
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BLTDDAT 000 A er d Blitter output data (from Blitter to RAM)
DMACONR 002 AP r p Read DMA control register
VPOSR 004 A r p MSB of vertical position
VHPOSR 006 A r p Vertical and horizontal beam position
DSKDATR 008 P er d Disk read data (from disk to RAM)
JOY0DAT 00A D r p Joystick/mouse position game port 0
JOY1DAT 00C D r p Joystick/mouse position game port 1
CLXDAT 00E D r p Collision register
ADKCONR 010 P r p Read audio/disk control register
POT1DAT 012 P r p Read potentiometer game port 0
POT1DAT 014 P r p Read potentiometer game port 1
POTGOR 016 P r p Readpot.portdata
SERDATR 018 P r p Read serial port and status
DSKBYTR 0lA P r p Read disk data byte and status
INTENAR 01C P r p Read interrupt enable
INTREQR 01E P r p Read interrupt request
DSKPTH 020 A w p Disk DMA address bits 18-20
DSKPTL 022 A w p Disk DMA address bits 1-15
DSKLEN 024 P w p Disk DMA block length
DSKDAT 026 P w d Disk write data (from RAM to disk)
REFPTR 028 A w d Refresh counter
VPOSW 02A A w p Write MSB of vertical beam position
VHPOSW 02C A w p Write vertical and horizontal beam position
COPCON 02E A w p Copper control register
SERDAT 030 P w p Write serial data and stop bits
SERPER 032 P w p Serial port control register and baud rate
POTGO 034 P w p Write pot. port data and start bit
JOYTEST 036 D w p Write in both mouse counters
STREQU 038 D s d Horizontal sync with VB and equal frame
STRVBL 03A D s d Horizontal sync with vertical blank
STRHOR 03C DP s d Horizontal synchronization signal
STRLONG 03E D s d Long horizontal line marker
BLTCONO 040 A w p Blitter control register 0
BLTCON1 042 A w p Blitter control register 1
BLTAFWM 044 A w p Mask for first data word from A
BLTALWM 046 A w p Mask for last data word from A
BLTCPTH 048 A w p Address of source data C bits 16-20
BLTCPTL 04A A w p Address of source data C bits 1-15
BLTBPTH 04C A w p Address of source data B bits 16-20
BLTBPTL 04E A w p Address of source data B bits 1-15
BLTAPTH 050 A w p Address of source data A bits 16-20
BLTAPTL 052 A w p Address of source data A bits 1-15
BLTDPTH 054 A w p Address of destination data D bits 16-20
BLTDPTL 056 A w p Address of destination data D bits 1-15
BLTSIZE 058 A w p Start bit and size of Blitter window
BLTCONOL 05A A w p Like BLTCON0, bits 0-7
BLTSIZEV 05C A w p Width of Blitter window
BLTSIZEH 05E A w p Height of Blitter window
BLTCMOD 060 A w p Blitter modulo for source data C
BLTBMOD 062 A w p Blitter modulo for source data B
BLTAMOD 064 A w p Blitter modulo for source data A
BLTDMOD 066 A w p Blitter modulo for destination data D
--- 068 Unused
--- 06A Unused
--- 06C Unused
--- 06E Unused
BLTCDAI 070 A w d Blitter source data register C
BLTBDAT 072 A w d Blitter source data register B
BLTADAT 074 A w d Blitter source data register A
--- 076 Unused
--- 078 Unused
--- 07A Unused
DENISEID 07C D r p Chip identification from Denise
DSKSYNC 07E P w p Disk sync pattern
COP1LCH 080 A w p Address of 1st Copper list bits 16-20
COP1LCL 082 A w p Address of 1st Copper list bits 1-15
COP2LCH 084 A w p Address of 2nd Copper list bits 16-20
COP2LCL 086 A w p Address of 2nd Copper list bits 1-15
COPJMP1 088 A s p Jump to start of 1st Copper list
COPJMP2 08A A s p Jump to start of 2nd Copper list
COPINS 08C A w d Copper command register
DIWSTRT 08E A w p Upper left corner of display window
DIWSTOP 090 A w p Lower right corner of display window
DDFSTRT 092 A w p Start of bit-plane DMA (horiz. pos.)
DDFSTOP 094 A w p End of bit-plane DMA (horiz. pos.)
DMACON 096 ADP w p Write DMA control register
CLXCON 098 D w p Write collision control register
INTENA 09A P w p Write interrupt enable
INTREQ 09C P w p Write interrupt request
ADKCON 09E P w p Audio, disk and UART control register
AUD0LCH 0A0 A w p Address of audio data bits 16-20
AUD0LCL 0A2 A w p On sound channel 0, bits 1-15
AUD0LEN 0A4 P w p Channel 0 length of audio data
AUD0PER 0A6 P w p Channel 0 period duration
AUD0VOL 0A8 P w p Channel 0 volume
AUD0DAT 0AA P w d Channel 0 audio data (to D/A converter)
--- 0AC Unused
--- 0AE Unused
AUD1LCH 0B0 A w p Address of audio data bits 16-20
AUD1LCL 0B2 A w p On sound channel 1, bits 1-15
AUD1LEN 0B4 P w p Channel 1 length of audio data
AUD1PER 0B6 P w p Channel 1 period duration
AUD1VOL 0B8 P w p Channel 1 volume
AUD1DAT 0BA P w d Channel 1 audio data (to D/A converter)
--- 0BC Unused
--- 0BE Unused
AUD2LCH 0C0 A w p Address of audio data bits 16-20
AUD2LCL 0C2 A w p On sound channel 2, bits 1-15
AUD2LEN 0C4 P w p Channel 2 length of audio data
AUD2PER 0C6 P w p Channel 2 period duration
AUD2VOL 0C8 P w p Channel 2 volume
AUD2DAT 0CA P w d Channel 2 audio data (to DIA converter)
--- 0CC Unused
--- 0CE Unused
AUD3LCH 0D0 A w p Address of audio data bits 16-20
AUD3LCL 0D2 A w p On sound channel 3, bits 1-15
AUD3LEN 0D4 P w p Channel 3 length of audio data
AUD3PER 0D6 P w p Channel 3 period duration
AUD3VOL 0D8 P w p Channel 3 volume
AUD3DAT 0DA P w d Channel 3 audio data (to D/A converter)
--- 0DC Unused
--- 0DE Unused
BPL1PTH 0E0 A w p Address of bit-plane 1, bits 16-20
BPL1PTL 0E2 A w p Address of bit-plane 1, bits 1-15
BPL2PTH 0E4 A w p Address of bit-plane 2, bits 16-20
BPL2PTL 0E6 A w p Address of bit-plane 2, bits~1 -15
BPL3PTH 0E8 A w p Address of bit-plane 3, bits 16-20
BPL3PTL 0EA A w p Address of bit-plane 3, bits 1-15
BPL4PTH 0EC A w p Address of bit-plane 4, bits 16-20
BPL4PTL 0EE A w p Address of bit-plane 4, bits 1-15
BPL5PTH 0F0 A w p Address of bit-plane 5, bits 16-20
BPL5PTL 0F2 A w p Address of bit-plane 5, bits 1-15
BPL6PTH 0F4 A w p Address of bit-plane 6, bits 16-20
BPL6PTL 0F6 A w p Address of bit-plane 6, bits 1-15
--- 0F8 Unused
--- 0FA Unused
--- 0FC Unused
--- 0FE Unused
BPLCON0 100 AD w p Bit-plane control register 0
BPLCON1 102 D w p Control register 1 (scroll values)
BPLCON2 104 D w p Control register 2 (priority control)
BPLCON3 106 D w p Control register 3
BPL1MOD 108 A w p Bit-plane modulo for uneven planes
BPL2MOD 10A A w p Bit-plane modulo for even planes
--- 10C Unused
--- 10E Unused
BPL1DAT 110 D w d Bit-plane 1 data (to RGB output)
BPL2DAT 112 D w d Bit-plane 2 data (to RGB output)
BPL3DAT 114 D w d Bit-plane 3 data (to RGB output)
BPL4DAT 116 D w d Bit-plane 4 data (to RGB output)
BPL5DAT 118 D w d Bit-plane 5 data (to RGB output)
BPL6DAT 11A D w d Bit-plane 6 data (to RGB output)
--- 11C Unused
--- 11E Unused
SPR0PTH 120 A w p Sprite data 0, bits 16-18
SPR0PTL 122 A w p Sprite data 0, bits 1-15
SPR1PTH 124 A w p Sprite data 1, bits 16-18
SPR1PTL 126 A w p Sprite data 1, bits 1-15
SPR2PTH 128 A w p Sprite data 2, bits 16-18
SPR2PTL 12A A w p Sprite data 2, bits 1-15
SPR3PTH 12C A w p Sprite data 3, bits 16-18
SPR3PTL 12E A w p Sprite data 3, bits 1-15
SPR4PTH 130 A w p Sprite data 4, bits 16-18
SPR4PTL 132 A w p Sprite data 4, bits 1-15
SPR5PTH 134 A w p Sprite data 5, bits 16-18
SPR5PTL 136 A w p Sprite data 5, bits 1-15
SPR6PTH 138 A w p Sprite data 6, bits 16-18
SPR6PTL 13A A w p Sprite data 6, bits 1-15
SPR7PTH 13C A w p Sprite data 7, bits 16-18
SPR7PTL 13E A w p Sprite data 7, bits 1-15
SPR0POS 140 AD w dp Sprite 0 start position (vert. and horiz.)
SPR0CTL 142 AD w dp Sprite 0 control reg. and vertical stop
SPR0DATA 144 D w dp Sprite 0 data register A (to RGB output)
SPR0DATB 146 D w dp Sprite 0 data register B (to RGB output)
SPR1POS 148 AD w dp Sprite 1 start position (vert. and horiz.)
SPR1CTL 14A AD w dp Sprite 1 control reg. and vertical stop
SPR1DATA 14C D w dp Sprite 1 data register A (to RGB output)
SPR1DATB 14E D w dp Sprite 1 data register B (to RGB output)
SPR2POS 150 AD w dp Sprite 2 start position (vert. and horiz.)
SPR2CTL 152 AD w dp Sprite 2 control reg. and vertical stop
SPR2DATA 154 D w dp Sprite 2 data register A (to RGB output)
SPR2DATB 156 D w dp Sprite 2 data register B (to RGB output)
SPR3POS 158 AD w dp Sprite 3 start position (vert. and horiz.)
SPR3CTL 15A AD w dp Sprite 3 control reg. and vertical stop
SPR3DATA 15C D w dp Sprite 3 data register A (to RGB output)
SPR3DATB 15E D w dp Sprite 3 data register B (to RGB output)
SPR4POS 160 AD w dp Sprite 4 start position (vert. and horiz.)
SPR4CTL 162 AD w dp Sprite 4 control reg. and vertical stop
SPR4DATA 164 D w dp Sprite 4 data register A (to RGB output)
SPR4DATB 166 D w dp Sprite 4 data register B (to RGB output)
SPR5POS 168 AD w dp Sprite 5 start position (vert. and horiz.)
SPR5CTL 16A AD w dp Sprite 5 control reg. and vertical stop
SPR5DATA l6C D w dp Sprite 5 data register A (to RGB output)
SPR5DATB 16E D w dp Sprite 5 data register B (to RGB output)
SPR6POS 170 AD w dp Sprite 6 start position (vert. and horiz.)
SPR6CTL 172 AD w dp Sprite 6 control reg. and vertiGal stop
SPR6DATA 174 D w dp Sprite 6 data register A (z. RGB output.)
SPR6DATB 176 D w dp Sprite 6 data register B (to RGB output)
SPR7POS 178 AD w dp Sprite 7 start position (vert. and horiz.)
SPR7CTL 17A AD w dp Sprite 7 control reg. and vertical stop
SPR7DATA 17C D w dp Sprite 7 data register A (to RGB output)
SPR7DATB 17E D w dp Sprite 7 data register B (to RGB output)
COLOR00 180 D w p Color palette register 0 (color table)
COLOR0l 182 D w p Color palette register 1 (color table)
COLOR02 184 D w p Color palette register 2 (color table)
COLOR03 186 D w p Color palette register 3 (color table)
COLOR04 188 D w p Color palette register 4 (color table)
COLOR05 18A D w p Color palette register 5 (color table)
COLOR06 18C D w p Color palette register 6 (color table)
COLOR07 18E D w p Color palette register 7 (color table)
COLOR08 190 D w p Color palette register 8 (color table)
COLOR09 192 D w p Color palette register 9 (color table)
COLOR10 194 D w p Color palette register 10 (color table)
COLOR11 196 D w p Color palette register 11 (color table)
COLOR12 198 D w p Color palette register 12 (color table)
COLOR13 19A D w p Color palette register 13 (color table)
COLOR14 19C D w p Color palette register 14 (color table)
COLOR15 19E D w p Color palette register 15 (color table)
COLOR16 lA0 D w p Color palette register 16 (color table)
COLOR17 1A2 D w p Color palette register 17 (color table)
COLOR18 1A4 D w p Color palette register 18 (color table)
COLOR19 1A6 D w p Color palette register 19 (color table)
COLOR20 1A8 D w p Color palette register 20 (color table)
COLOR21 1AA D w p Color palette register 21 (color table)
COLOR22 lAC D w p Color palette register 22 (color table)
COLOR23 1AE D w p Color palette register 23 (color table)
COLOR24 1B0 D w p Color palette register 24 (color table)
COLOR25 1B2 D w p Color palette register 25 (color table)
COLOR26 1B4 D w p Color palette register 26 (color table)
COLOR27 1B6 D w p Color palette register 27 (color table)
COLOR28 1B8 D w p Color palette register 28 (color table)
COLOR29 1BA D w p Color palette register 29 (color table)
COLOR30 1BC D w p Color palette register 30 (color table)
COLOR31 1BE D w p Color palette register 31 (color table)
HTOTAL 1C0 A w p Clock count per line (VARBEAM=1)
HSSTOP 1C2 A w p H-sync stop position
HBSTRT 1C4 A w p H-blank start position
HBSTOP 1C6 A w p H-blank stop position
VTOTAL 1C8 A w p Number of lines per picture
VSSTOP 1CA A w p V-sync stop line
VBSTRT 1CC A w p V-blank start line
VBSTOP ICE A w p V-blank stop line
SPRHSTRT 1D0 A w p UHRES sprite start line
SPRHSTOP 1D2 A w p UHRES sprite stop line
BPLHSTRT 1D4 A w p UHRES bit-plane start line
BPLHSTOP 1D6 A w p UHRES bit-plane stop line
HHPOSW 1D8 A w p Write DUAL-mode column counter
HHPOSR 1DA A r p Read DUAL-mode column counter
BEAMCON0 1DC A w p Raster beam control register
HSSTRT 1DE A w p H-sync start position
VSSTRT lE0 A w p V-sync start position
HCENTER 1E2 A w p H-pos. of V-sync in interlace mode
DIWHIGH 1E4 A,D w p Screen window, upper bits for start/stop
BPLHMOD 1E6 A w p UHRES bit-plane modulo
SPRHPTH 1E8 A w p UHRES sprite pointer (bits 16-20)
SPRHPTL lEA A w p UHRES sprite pointer (bits 0-15)
BPLHPTH lEC A w p UHRES bit-plane pointer (bits 16-20)
BPLHPTL lEE A w p UHRES bit-plane pointer (bits 0-15)
The registers 1F0 to 1FC are unoccupied
Written & Compiled By Paul Andrews JR
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